10 Gb/s to 40 Gb/s Receiver for High-Density Optical Interconnects in 80-nm CMOS (Series in Microelectronics)
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10 Gb/s to 40 Gb/s Receiver for High-Density Optical Interconnects in 80-nm CMOS (Series in Microelectronics) (2006)
EN PB NW FE
ISBN: 9783866280694 bzw. 3866280696, in Englisch, 270 Seiten, Hartung-Gorre, Taschenbuch, neu, Erstausgabe.
Lieferung aus: Deutschland, Versandfertig in 1 - 2 Werktagen, Versandkostenfrei. Tatsächliche Versandkosten können abweichen.
Von Händler/Antiquariat, hartung_gorre_verlag.
This book presents several circuits for 10 Gb/s to 40 Gb/s low power, high-density optical interconnect applications implemented in a standard digital 80-nm CMOS process. With a 4×10 Gb/s optical transceiver array, consuming 2.5 mW/(Gb/s) only, it was demonstrated that the required aggregate bandwidth of several Tb/s in near future and the limited system power budget in high-density chip-to-chip interconnects can be met. A 40 Gb/s optical receiver explores the possibilities in terms of high speed and low power consumption of today's CMOS technology. In order to achieve these high data rates of the optical receivers, a novel transimpedance amplifier (TIA) topology is introduced and compact peaking inductors were used. A first-order bang-bang clock-and-data recovery (CDR) circuit presents a high data rate of 25 Gb/s and a new topology suited for high-density, pseudo-synchronous electrical and optical interconnects. In addition, a detailed system analysis for an optical link is given and electrical specifications for the receiver designs are derived. Further, CMOS NFET transistors are characterized for DC, AC and noise performance, and many new circuit ideas and topologies are proposed. Keywords: Receiver, transceiver, transceiver array, transmitter, optical, optical receiver, high-density, interconnect, array, IO, I/O, I-O, link, data communication, 10 Gb/s, 10 Gbps, 10 GHz, 20 Gb/s, 20 Gbps, 20 GHz, 25 Gb/s, 25 Gbps, 25 GHz, 40 Gb/s, 40 Gbps, 40 GHz, transimpedance amplifier, TIA, limiting amplifier, LA, buffer, output buffer, broadband amplifier, feedback, feedback amplifier, shunt-feedback, feed-forward, common-gate, regulated cascode, small-signal, transimpedance, operational transconductance amplifier, OTA, DC-offset, compensation, common-mode feedback, CMFB, Clock-and-data recovery, CDR, static frequency divider, dynamic frequency divider, phase interpolator, clock buffer, half-rate phase detector, analog filter, digital loop filter, D-flip-flop, DFF, Taschenbuch, Ausgabe: 1., Label: Hartung-Gorre, Hartung-Gorre, Produktgruppe: Book, Publiziert: 2006-04-01, Studio: Hartung-Gorre, Verkaufsrang: 4275745.
Von Händler/Antiquariat, hartung_gorre_verlag.
This book presents several circuits for 10 Gb/s to 40 Gb/s low power, high-density optical interconnect applications implemented in a standard digital 80-nm CMOS process. With a 4×10 Gb/s optical transceiver array, consuming 2.5 mW/(Gb/s) only, it was demonstrated that the required aggregate bandwidth of several Tb/s in near future and the limited system power budget in high-density chip-to-chip interconnects can be met. A 40 Gb/s optical receiver explores the possibilities in terms of high speed and low power consumption of today's CMOS technology. In order to achieve these high data rates of the optical receivers, a novel transimpedance amplifier (TIA) topology is introduced and compact peaking inductors were used. A first-order bang-bang clock-and-data recovery (CDR) circuit presents a high data rate of 25 Gb/s and a new topology suited for high-density, pseudo-synchronous electrical and optical interconnects. In addition, a detailed system analysis for an optical link is given and electrical specifications for the receiver designs are derived. Further, CMOS NFET transistors are characterized for DC, AC and noise performance, and many new circuit ideas and topologies are proposed. Keywords: Receiver, transceiver, transceiver array, transmitter, optical, optical receiver, high-density, interconnect, array, IO, I/O, I-O, link, data communication, 10 Gb/s, 10 Gbps, 10 GHz, 20 Gb/s, 20 Gbps, 20 GHz, 25 Gb/s, 25 Gbps, 25 GHz, 40 Gb/s, 40 Gbps, 40 GHz, transimpedance amplifier, TIA, limiting amplifier, LA, buffer, output buffer, broadband amplifier, feedback, feedback amplifier, shunt-feedback, feed-forward, common-gate, regulated cascode, small-signal, transimpedance, operational transconductance amplifier, OTA, DC-offset, compensation, common-mode feedback, CMFB, Clock-and-data recovery, CDR, static frequency divider, dynamic frequency divider, phase interpolator, clock buffer, half-rate phase detector, analog filter, digital loop filter, D-flip-flop, DFF, Taschenbuch, Ausgabe: 1., Label: Hartung-Gorre, Hartung-Gorre, Produktgruppe: Book, Publiziert: 2006-04-01, Studio: Hartung-Gorre, Verkaufsrang: 4275745.
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10 Gb/s to 40 Gb/s Receiver for High-Density Optical Interconnects in 80-nm CMOS (Series in Microelectronics) (2006)
EN PB US FE
ISBN: 9783866280694 bzw. 3866280696, in Englisch, 270 Seiten, Hartung-Gorre, Taschenbuch, gebraucht, Erstausgabe.
Lieferung aus: Deutschland, Versandfertig in 1 - 2 Werktagen, Versandkostenfrei. Tatsächliche Versandkosten können abweichen.
Von Händler/Antiquariat, online-buch-de.
This book presents several circuits for 10 Gb/s to 40 Gb/s low power, high-density optical interconnect applications implemented in a standard digital 80-nm CMOS process. With a 4×10 Gb/s optical transceiver array, consuming 2.5 mW/(Gb/s) only, it was demonstrated that the required aggregate bandwidth of several Tb/s in near future and the limited system power budget in high-density chip-to-chip interconnects can be met. A 40 Gb/s optical receiver explores the possibilities in terms of high speed and low power consumption of today's CMOS technology. In order to achieve these high data rates of the optical receivers, a novel transimpedance amplifier (TIA) topology is introduced and compact peaking inductors were used. A first-order bang-bang clock-and-data recovery (CDR) circuit presents a high data rate of 25 Gb/s and a new topology suited for high-density, pseudo-synchronous electrical and optical interconnects. In addition, a detailed system analysis for an optical link is given and electrical specifications for the receiver designs are derived. Further, CMOS NFET transistors are characterized for DC, AC and noise performance, and many new circuit ideas and topologies are proposed. Keywords: Receiver, transceiver, transceiver array, transmitter, optical, optical receiver, high-density, interconnect, array, IO, I/O, I-O, link, data communication, 10 Gb/s, 10 Gbps, 10 GHz, 20 Gb/s, 20 Gbps, 20 GHz, 25 Gb/s, 25 Gbps, 25 GHz, 40 Gb/s, 40 Gbps, 40 GHz, transimpedance amplifier, TIA, limiting amplifier, LA, buffer, output buffer, broadband amplifier, feedback, feedback amplifier, shunt-feedback, feed-forward, common-gate, regulated cascode, small-signal, transimpedance, operational transconductance amplifier, OTA, DC-offset, compensation, common-mode feedback, CMFB, Clock-and-data recovery, CDR, static frequency divider, dynamic frequency divider, phase interpolator, clock buffer, half-rate phase detector, analog filter, digital loop filter, D-flip-flop, DFF, Taschenbuch, Ausgabe: 1., Label: Hartung-Gorre, Hartung-Gorre, Produktgruppe: Book, Publiziert: 2006-04-01, Studio: Hartung-Gorre, Verkaufsrang: 4275745.
Von Händler/Antiquariat, online-buch-de.
This book presents several circuits for 10 Gb/s to 40 Gb/s low power, high-density optical interconnect applications implemented in a standard digital 80-nm CMOS process. With a 4×10 Gb/s optical transceiver array, consuming 2.5 mW/(Gb/s) only, it was demonstrated that the required aggregate bandwidth of several Tb/s in near future and the limited system power budget in high-density chip-to-chip interconnects can be met. A 40 Gb/s optical receiver explores the possibilities in terms of high speed and low power consumption of today's CMOS technology. In order to achieve these high data rates of the optical receivers, a novel transimpedance amplifier (TIA) topology is introduced and compact peaking inductors were used. A first-order bang-bang clock-and-data recovery (CDR) circuit presents a high data rate of 25 Gb/s and a new topology suited for high-density, pseudo-synchronous electrical and optical interconnects. In addition, a detailed system analysis for an optical link is given and electrical specifications for the receiver designs are derived. Further, CMOS NFET transistors are characterized for DC, AC and noise performance, and many new circuit ideas and topologies are proposed. Keywords: Receiver, transceiver, transceiver array, transmitter, optical, optical receiver, high-density, interconnect, array, IO, I/O, I-O, link, data communication, 10 Gb/s, 10 Gbps, 10 GHz, 20 Gb/s, 20 Gbps, 20 GHz, 25 Gb/s, 25 Gbps, 25 GHz, 40 Gb/s, 40 Gbps, 40 GHz, transimpedance amplifier, TIA, limiting amplifier, LA, buffer, output buffer, broadband amplifier, feedback, feedback amplifier, shunt-feedback, feed-forward, common-gate, regulated cascode, small-signal, transimpedance, operational transconductance amplifier, OTA, DC-offset, compensation, common-mode feedback, CMFB, Clock-and-data recovery, CDR, static frequency divider, dynamic frequency divider, phase interpolator, clock buffer, half-rate phase detector, analog filter, digital loop filter, D-flip-flop, DFF, Taschenbuch, Ausgabe: 1., Label: Hartung-Gorre, Hartung-Gorre, Produktgruppe: Book, Publiziert: 2006-04-01, Studio: Hartung-Gorre, Verkaufsrang: 4275745.
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Symbolbild
10 Gb/s to 40 Gb/s Receiver for High-Density Optical Interconnects in 80-nm CMOS (Series in Microelectronics) Kromer, Christian
DE
ISBN: 9783866280694 bzw. 3866280696, in Deutsch.
Von Händler/Antiquariat, Lux Libris [51657365], Dozwil, Switzerland.
Widmung und Autogramm des Autors am Vorsatzblatt, wie ungebraucht (211-1).
Widmung und Autogramm des Autors am Vorsatzblatt, wie ungebraucht (211-1).
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